7

ICS1524A

ICS1524A Rev F 05/13/10

Name:

Loop Control Register

Register:

1h

Index:

Read / Write*

Bit Name Bit #

Reset Value

Description

PFD0 -2

0 - 2

0

Charge Pump Gain

Reserved

3

0

Reserved

PSD 0-1

4 - 5

0

Post-Scaler Divider

Reserved

6 -7

0

Reserved

Bit

Name

Description

0-2

PFD0-2

Charge Pump Gain

3

Reserved

4-5

PSD 0-1

Post-Scaler Divider — Divides the output of the VCO to the DPA and Feedback Divider.

6-7

Reserved

*Double-buffered register. Actual working registers are loaded during software PLL reset.

See register 8h for details.

2

t

i

B1

t

i

B0

t

i

B2

/

A

µ

(

n

i

a

G

CP

π

)

d

a

r

000

1

00

1

2

01

0

4

01

1

8

10

0

6

1

10

1

2

3

11

0

4

6

111

8

2

1

5

t

i

B4

t

i

Br

e

d

i

v

i

D

D

S

P

00

)

t

l

u

a

f

e

d

(

2

01

4

10

8

11

6

1