ICS1524AMLF datasheet(10/25 Pages) RENESAS

10 / 25 page

ICS1524A

Name:

Output Enable Register

6 h

Index:

Read / Write

Bit Name Bit #

Reset Value

Description

OE_Pck

Output Enable for DPACLK Outputs (PECL, Pins 21, 20 )

OE_Tck

Output Enable for DPACLK Output (SSTL_3 Pin 17)

OE_P2

Output Enable for CLK Outputs (PECL, Pins 23, 22)

OE_T2

Output Enable for CLK Output (SSTL_3, Pin 16)

OE_F

Output Enable for FUNC Output (SSTL_3, Pin 15)

CK2_Inv

Select CLK Output Source (Pins 23, 22, 16)

Out_Scl

6-7

DPACLK Output Scaler (SSTL_3, Pin 17)

Bit

Name

Description

OE_Pck

Output Enable for DPACLK Outputs (PECL)

0 = High Z

1 = Enabled

OE_Tck

Output Enable for DPACLK Output (SSTL_3)

0 = High Z

1 = Enabled

OE_P2

Output Enable for CLK Outputs (PECL)

0 = High Z

1 = Enabled

OE_T2

Output Enable for CLK Output (SSTL_3)

0 = High Z

1 = Enabled

OE_F

Output Enable for FUNC Output (SSTL_3)

0 = High Z

1 = Enabled

Ck2_Inv

Select CLK Output Source (Pins 23, 22, 16)

0 = Half Speed DPA Delayed clock to CLK outputs

1 = Full Speed non-DPA Delayed clock to CLK outputs

6 -7

Out_Scl

Clock (DPACLK, pin 17) Scaler

DPACLK Divider

Bit 7

Bit 6

ICS1524AMLF Datasheet(PDF) 10 Page - Renesas Technology Corp

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