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ICS1524AMLF Datasheet(PDF) 1 Page - Renesas Technology Corp

Part # ICS1524AMLF
Description  Dual Output Phase Controlled SSTL_3/PECL Clock Generator
PDF  25 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS1524AMLF Datasheet(HTML) 1 Page - Renesas Technology Corp

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General Description
Features
ICS1524A
Block Diagram
Dual Output Phase Controlled SSTL_3/PECL Clock Generator
•
Wide input frequency range
• 8 kHz to 100 MHz
•
250 MHz balanced PECL differential outputs
•
150 MHz single-ended SSTL_3 clock outputs
•
Dynamic Phase Adjust (DPA) for DPACLK
outputs
• Software controlled phase adjustment
• 360
o Adjustment down to 1/64 clock
increments
•
External or internal loop filter selection
•
Uses 3.3 VDC Inputs are 5 volt tolerant.
•I
2C-bus serial interface runs at either low speed
(100 kHz) or high speed (400 kHz).
•
Hardware and Software PLL Lock detection
The ICS1524A is a low-cost, very high-performance
frequency generator and phase controlled clock synthe-
sizer. It is perfectly suited to phase controlled clock
synthesis and distribution as well as line-locked and
genlocked applications.
The ICS1524A offers two channels of clock phase con-
trolled outputs; CLK and DPACLK. These two output
channels have both 250 MHz PECL differential and 150
MHz SSTL_3 single-ended output pins. The CLK output
channel has a fixed phase relationship to the PLL’s input
and the DPACLK uses the Dynamic Phase Adjust cir-
cuitry to allow control of the clock phase relative to input
signal.
Optionally, the CLK outputs can operate at half the clock
rate and phase aligned with the DPACLK channel, en-
abling deMUXing of multiplexed analog-to-digital
converters. The FUNC pin provides either the regener-
ated input from the phase-locked loop (PLL) divider
chain output or a re-synchronized and sharpened input
HSYNC.
The advanced PLL uses either its internal program-
mable feedback divider or an external divider and is
programmed by a standard I
2C-bus™ serial interface.
I
2
C-bus is a trademark of Philips Corporation.
Applications
•
Generic Frequency Synthesis
•
LCD Monitors and Projectors
•
Genlocking Multiple Video Systems
HSYNC
OSC
IC
2
DPACLK+/-
FUNC
DPACLK
Loop
Filter
CLK+/-
CLK
Pin Configuration
24 Pin 300-mil SOIC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDDD
VSSD
SDA
SCL
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
IREF
CLK+
(PECL)
C
VSSQ
VDDQ
CLK
(SSTL)
CLK
(SSTL)
FUNC
(SSTL)
LOCK/REF (SSTL)
ICADR
LK–
(PECL)
DPACLK+ (PECL)
DPACLK– (PECL)
DPA
2


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