PSD4235G2V-10UI datasheet(61/100 Pages) STMICROELECTRONICS

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PSD4256G6V

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

Table 40. Port Operating Mode Settings

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

3. Any of these three methods enables the JTAG pins on Port E.

4. Control Register setting is not applicable to Ports A, B and C.

Table 41. I/O Port Latched Address Output Assignments

Note: 1. N/A = Not Applicable.

Mode

Defined in PSDsoft

Control

Setting

Direction

Setting

VM Register

Setting

JTAG Enable

MCU I/O

Declare pins only

0 (Note 4)

1 = output,

0 = input

(Note 2)

N/A

PLD I/O

Declare pins and

Logic equations

N/A

(Note 2)

N/A

Data Port (Port F, G)

Selected for MCU

with non-multiplexed

bus

N/A

Address Out

(Port E, F, G)

Declare pins only

1 (Note 2)

N/A

Address In

(Port A, B, C, D, F)

Declare pins or Logic

equation for Input

Macrocells

N/A

Peripheral I/O

(Port F)

Logic equations

(PSEL0 and PSEL1)

N/A

PIO bit = 1

N/A

JTAG ISP 3

Declare pins only

N/A

JTAG_Enable

MCU RESET Mode

Specific pin logic

level

N/A

MCU

Port E

(PE3-PE0)

Port E

(PE7-PE4)

Port F

(PF3-PF0)

Port F

(PF7-PF4)

Port G

(PG3-PG0)

Port G

(PG7-PG4)

80C51XA

N/A(1)

Address

a7-a4

N/A

Address

a7-a4

Address

a11-a8

Address

a15-a12

All Other

MCUs with Multiplexed Bus

Address

a3-a0

Address

a7-a4

Address

a3-a0

Address

a7-a4

Address

a11-a8

(a3-a0 for 8-

bit MCU)

Address

a15-a12

(a7-a4 for 8-

bit MCU)

PSD4235G2V-10UI Datasheet(PDF) 61 Page - STMicroelectronics

PSD4235G2V-10UI Datasheet(HTML) 61 Page - STMicroelectronics

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