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JS28F320J3F75 Datasheet(PDF) 46 Page - Numonyx B.V |
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JS28F320J3F75 Datasheet(HTML) 46 Page - Numonyx B.V |
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46 / 67 page ![]() Datasheet 45 Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) 9.8.8 VPEN Protection When it’s necessary to protect the entire array, global protection can be achieved using a hardware mechanism using VPEN. Whenever a valid voltage is present on VPEN, blocks within the main flash array can be erased or programmed. By grounding VPEN, blocks within the main array cannot be altered – attempts to program or erase blocks will fail resulting in the setting of the appropriate error bit in the Status Register. By holding VPEN low, absolute write protection of all blocks in the array can be achieved. Table 31: Word-Wide Protection Register Addressing Word Use A8 A7A6 A5A4 A3A2A1 LOCK Both 10 00 00 00 0 Factory 10 00 00 01 1 Factory 10 00 00 10 2 Factory 10 00 00 11 3 Factory 10 00 01 00 4 User 1 00 00 10 1 5 User 1 00 00 11 0 6 User 1 00 00 11 1 7 User 1 00 01 00 0 Note: All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.) Table 32: Byte-Wide Protection Register Addressing Byte Use A8 A7A6A5A4 A3A2A1 A0 LOCK Both 1 000 000 00 LOCK Both 1 000 000 01 0 Factory 1 000 000 10 1 Factory 1 000 000 11 2 Factory 1 000 001 00 3 Factory 1 000 001 01 4 Factory 1 000 001 10 5 Factory 1 000 001 11 6 Factory 1 000 010 00 7 Factory 1 000 010 01 8 User 1 000 010 10 9 User 1 000 010 11 A User 1 000 011 00 B User 1 000 011 01 C User 1 000 011 10 D User 1 000 011 11 E User 1 000 100 00 F User 1 000 100 01 Note: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A[MAX:9] = 0. |
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