723634L15PFG datasheet(3/35 Pages) RENESAS

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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Communication between each port may bypass the FIFOs via two

mailboxregisters.ThemailboxregisterwidthmatchestheselectedPortBbus

width.EachMailboxregisterhasaflag(MBF1andMBF2)tosignalwhennew

mailhasbeenstored.

TwokindsofresetareavailableontheseFIFOs:MasterResetandPartial

Reset.MasterResetinitializesthereadandwritepointerstothefirstlocation

of the memory array, configures the FIFO for Big- or Little-Endian byte

arrangementandselectsserialflagprogramming,parallelflagprogramming,

oroneofthreepossibledefaultflagoffsetsettings,8,16or64.Therearetwo

Master Reset pins, MRS1 and MRS2.

PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe

memory.UnlikeMasterReset,anysettingsexistingpriortoPartialReset(i.e.,

programmingmethodandpartialflagdefaultoffsets)areretained.PartialReset

is useful since it permits flushing of the FIFO memory without changing any

configurationsettings.EachFIFOhasitsown,independentPartialResetpin,

PRS1 and PRS2.

Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,

the first word written to an empty FIFO is deposited into the memory array. A

read operation is required to access that word (along with all other words

residing in memory). In the First Word Fall Through mode (FWFT), the first

long-word(36-bitwide)writtentoanemptyFIFOappearsautomaticallyonthe

outputs,noreadoperationisrequired(nevertheless,accessingsubsequent

wordsdoesnecessitateaformalreadrequest).ThestateoftheBE/FWFTpin

during FIFO operation determines the mode in use.

Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and

EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB).

TheEFandFFfunctionsareselectedintheIDTStandardmode.EFindicates

whether or not the FIFO memory is empty. FF shows whether the memory is

fullornot.TheIRandORfunctionsareselectedintheFirstWordFallThrough

mode.IRindicateswhetherornottheFIFOhasavailablememorylocations.

ORshowswhethertheFIFOhasdataavailableforreadingornot.Itmarksthe

presence of valid data on the outputs.

EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and

aprogrammableAlmost-Fullflag(AFAandAFB). AEAandAEB indicatewhen

aselectednumberofwordsremainintheFIFOmemory.AFAandAFBindicate

when the FIFO contains more than a selected number of words.

FFA/IRA,FFB/IRB,AFAandAFBaretwo-stagesynchronizedtotheport

clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are

two-stage synchronized to the port clock that reads data from its array.

ProgrammableoffsetsforAEA,AEB,AFAandAFBareloaded inparallelusing

Port A or in serial via the SD input. The Serial Programming Mode pin (SPM)

makesthisselection.Threedefaultoffsetsettingsarealsoprovided.TheAEA

andAEBthresholdcanbesetat8,16or64locationsfromtheemptyboundary

andtheAFAandAFBthresholdcanbesetat8,16or64locationsfromthefull

boundary. All these choices are made using the FS0 and FS1 inputs during

MasterReset.

Two or more devices may be used in parallel to create wider data

paths. If, at any time, the FIFO is not actively performing a function, the chip

will automatically power down. During the power down state, supply current

consumption (ICC) is at a minimum. Initiating any operation (by activating

control inputs) will immediately take the device out of the power down state.

The IDT723624/723634/723644 are characterized for operation from

0°Cto70°C.Industrial temperaturerange(-40

°Cto+85°C)isavailable.They

arefabricatedusinghighspeed,submicronCMOStechnology.

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