723634L15PFG datasheet(14/35 Pages) RENESAS

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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle

can be the first synchronization cycle (see Figures 15, 16, 17, and 18).

FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)

Thisisadualpurposeflag.InFWFTmode,theInputReady(IRAandIRB)

function is selected. In IDT Standard mode, the Full Flag (FFA and FFB)

functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis

HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory

locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites

to the FIFO are ignored.

The Full/Input Ready flag of a FlFO is synchronized to the port clock that

writes data to its array. For both FWFT and IDT Standard modes, each time

awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine

thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer

comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2.

FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready

to be written to in a minimum of two cycles of the Full/Input Ready flag

synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than

twocyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsince

the next memory write location has been read. The second LOW-to-HIGH

transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets

the Full/Input Ready flag HIGH.

ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock

beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat

time tSKEW1 orgreateraftertheread.Otherwise,thesubsequentclockcycle

can be the first synchronization cycle (see Figures 19, 20, 21, and 22).

ALMOST-EMPTY FLAGS (AEA, AEB)

TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads

data from its array. The state machine that controls an Almost-Empty flag

monitorsawritepointerandreadpointercomparatorthatindicateswhenthe

FIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.

Thealmost-emptystateisdefinedbythecontentsofregisterX1for AEBand

FIFO reset, programmed from Port A, or programmed serially (see Almost-

Empty flag and Almost-Full flag offset programming section). An Almost-

EmptyflagisLOWwhenitsFIFOcontainsXorlesswordsandisHIGHwhen

itsFIFOcontains(X+1)ormorewords.AdatawordpresentintheFIFOoutput

TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock

arerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenewlevel

offill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormorewords

remains LOW if two cycles of its synchronizing clock have not elapsed since

thewritethatfilledthememorytothe(X+1)level.AnAlmost-Emptyflagisset

HIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter

theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransition

ofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronization

cycleifitoccursattimetSKEW2 orgreaterafterthewritethatfillstheFIFOto(X+1)

words.Otherwise,thesubsequentsynchronizingclockcyclemaybethefirst

synchronization cycle. (See Figures 23 and 24).

ALMOST-FULL FLAGS (AFA, AFB)

TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites

datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitors

a write pointer and read pointer comparator that indicates when the FIFO

memorystatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate

isdefinedbythecontentsofregisterY1forAFAandregisterY2forAFB.These

registersareloadedwithpresetvaluesduringaFlFOreset,programmedfrom

Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag

offsetprogrammingsection).AnAlmost-FullflagisLOWwhenthenumberof

words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y)

for the IDT723624, IDT723634, or IDT723644 respectively. An Almost-Full

flagisHIGHwhenthenumberofwordsinitsFIFOislessthanorequalto[256-

(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723624, IDT723634, or

IDT723644 respectively. Note that a data word present in the FIFO output

TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock

are required after a FIFO read for its Almost-Full flag to reflect the new level

of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-

(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave

notelapsedsincethereadthatreducedthenumberofwordsinmemoryto[256/

512/1,024-(Y+1)].AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH

transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber

of words in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH transition of

anAlmost-Fullflagsynchronizingclockbeginsthefirstsynchronizationcycle

if it occurs at time tSKEW2 or greater after the read that reduces the number of

words in memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent

synchronizingclockcyclemaybethefirstsynchronizationcycle(seeFigures

25 and 26).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command and control

informationbetweenPortAandPortBwithoutputtingitinqueue.TheMailbox

select (MBA, MBB) inputs choose between a mail register and a FIFO for a

port data transfer operation. The usable width of both the Mail1 and Mail2

registers matches the selected bus size for Port B.

ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen

a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the

selectedPortBbussizeisalso36bits,thentheusablewidthoftheMail1register

employs data lines A0-A35. If the selected Port B bus size is 18 bits, then the

usable width of the Mail1 Register employs data lines A0-A17. (In this case,

A18-A35 are don’t care inputs.) If the selected Port B bus size is 9 bits, then

theusablewidthoftheMail1RegisteremploysdatalinesA0-A8.(Inthiscase,

A9-A35 are don’t care inputs.)

A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2

HIGH. If the selected Port B bus size is also 36 bits, then the usable width of

theMail2employsdatalinesB0-B35.IftheselectedPortBbussizeis18bits,

thentheusablewidthoftheMail2RegisteremploysdatalinesB0-B17.(Inthis

case, B18-B35 are don’t care inputs.) If the selected Port B bus size is 9 bits,

thentheusablewidthoftheMail1RegisteremploysdatalinesB0-B8.(Inthis

case, B9-B35 are don’t care inputs.)

Writingdatatoamailregistersetsitscorrespondingflag(MBF1 orMBF2)

LOW.AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.

Whendataoutputsofaportareactive,thedataonthebuscomesfromthe

FIFO output register when the port Mailbox select input is LOW and from the

mail register when the port Mailbox select input is HIGH.

TheMail1RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransition

on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB

HIGH.Fora36-bitbussize,36bitsofmailboxdataareplacedonB0-B35.For

an18-bitbussize,18bitsofmailboxdataareplacedonB0-B17.(Inthiscase,

B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are

placed on B0-B8. (In this case, B9-B35 are indeterminate.)

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