32

COMMERCIALTEMPERATURERANGE

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Figure 26. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)

Figure 27. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)

NOTE:

1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35 will be

indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data

(B9-B35 will be indeterminate).

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge

and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.

2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.

3. D = Maximum FIFO Depth = 256 for the IDT723624, 512 for the IDT723634, 1,024 for the IDT723644.

4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.

AFB

CLKB

ENA

3270 drw28

ENB

CLKA

12

tSKEW2

tENH

tPAF

tENS2

tENH

tPAF

[D-(Y2+1)] Words in FIFO2

(D-Y2) Words in FIFO2

(1)

tENS2

3270 drw29

CLKA

ENA

A0-A35

MBA

CSA

W/

RA

CLKB

MBF1

CSB

MBB

ENB

B0-B35

W/RB

W1

tENS1

tENH

tDS

tDH

tPMF

tPMF

tENS2

tENH

tDIS

tEN

tMDV

tPMR

FIFO1 Output Register

W1 (Remains valid in Mail1 Register after read)

tENH

tENH

tENH

tENS1

tENS2

tENS2