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DSC-3270/6

© 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

MARCH 2018

IDT723624

IDT723634

IDT723644

CMOS SyncBiFIFOTM WITH BUS-MATCHING

256 x 36 x 2,

512 x 36 x 2,

1,024 x 36 x 2

IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIALTEMPERATURERANGE

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

••••• Memory storage capacity:

IDT723624 – 256 x 36 x 2

IDT723634 – 512 x 36 x 2

IDT723644 – 1,024 x 36 x 2

••••• Clock frequencies up to 67 MHz (10 ns access time)

••••• Two independent clocked FIFOs buffering data in opposite

directions

••••• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRB flag functions)

••••• Programmable Almost-Empty and Almost-Full flags; each has

three default offsets (8, 16 and 64)

••••• Serial or parallel programming of partial flags

••••• Port B bus sizing of 36-bits (long word), 18-bits (word) and

9-bits (byte)

••••• Big- or Little-Endian format for word and byte bus sizes

••••• Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

••••• Mailbox bypass registers for each FIFO

••••• Free-running CLKA and CLKB may be asynchronous or coinci-

dent (simultaneous reading and writing of data on a single clock

edge is permitted)

••••• Auto power down minimizes power dissipation

••••• Available in space saving 128-pin Thin Quad Flatpack (TQFP)

••••• Green parts available, see ordering information

Mail 1

Register

Programmable Flag

Offset Registers

RAM ARRAY

256 x 36

512 x 36

1,024 x 36

Write

Pointer

Read

Pointer

Status Flag

Logic

RAM ARRAY

256 x 36

512 x 36

1,024 x 36

Write

Pointer

Read

Pointer

Status Flag

Logic

CLKA

CSA

W/

RA

ENA

MBA

Port-A

Control

Logic

FIFO1,

Mail1

Reset

Logic

MRS1

Mail 2

Register

MBF2

CLKB

CSB

W/RB

ENB

MBB

BE

BM

SIZE

Port-B

Control

Logic

FIFO2,

Mail2

Reset

Logic

MRS2

MBF1

FIFO1

FIFO2

10

EFB/ORB

AEB

36

36

FFB/IRB

AFB

B0-B35

FFA/IRA

AFA

SPM

FS0/SD

FS1/

SEN

A0-A35

EFA/ORA

AEA

3270 drw01

36

36

PRS2

PRS1

Timing

Mode

FWFT

36

36

36

36