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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 65

Figure 71:

PLL_MULT, PLL_WRAP_MAIN_DIV, PLL_WRAP_ADC_DIV and RG_CTRL Calculation

Target Output Data Rate

PLL_WRAP_MAIN_DIV

PLL_WRAP_ADC_DIV

RG_CTRL

250

– 375 Mbit/s

IMG.1-5,7: 3

IMG.1-3: 3

IMG.4-5: 2

IMG.7: 3

IMG.1-3: 1

IMG.4-5: 11

IMG.7: 1

375

– 475 Mbit/s

IMG.1-5,7: 2

IMG.1-3: 2

IMG.4-5: 1

IMG.7: 2

IMG.1-3: 11

IMG.4-5: 21

IMG.7: 11

475

– 750 Mbit/s

IMG.1-5,7: 2

IMG.1-3: 2

IMG.4-5: 1

IMG.7: 2

IMG.1-3: 11

IMG.4-5: 21

IMG.7: 11

750

– 1000 Mbit/s

IMG.1-5,7: 1

IMG.1-3: 1

IMG.4-5: 0

IMG.7: 1

IMG.1-3: 21

IMG.4-5: 31

IMG.7: 21

1000

– 1250 Mbit/s

IMG.1-3,7: 1

IMG.4-5,

IMG.1-3: 1

IMG.4-5: NA

IMG.7: 1

IMG.1-3: 21

IMG.4-5: NA

IMG.7: 21

The parameters PLL_WRAP_ADC_DIV and RG_CTRL depend on the targeted output data rate as

shown in the table above.

The effective data rate is calculated with the following formula:

Equation 2:

��_��_�� [��] =

��_��[��] ∙ ��_��

2��_��_��_��

Note that due to the flooring operation in calculating the parameters, the targeted data cannot be

reached exactly for every possible input clock frequency (see example 1 below).

Figure 72:

Calculation Examples

Parameter

Example 1

Example 2

Image mode

IMG.4

fclk_in

12 MHz

12.5 MHz

Targeted data rate

700 Mbit/s

1000 Mbit/s

PLL_WRAP_ADC_DIV

PLL_WRAP_MAIN_DIV

PLL_DIV

233

160

CSG14K_CSG8K Datasheet(PDF) 66 Page - ams AG

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