CSG14K_CSG8K datasheet(79/113 Pages) AMSCO

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 78

Figure 92:

Valid Row Addresses

Region

Row Address Range (14 K)

Row Address Range (8 K)

Active pixels

60 … 3659

772 … 2947

Recommended pixels

68 … 3651

780 … 2939

Bottom buffer pixels

0 … 59

Top buffer pixels

3660 … 3719

ROI Settings

The sensor allows up to 10 vertical windows to be concatenated in one single frame readout.

Each of these windows is enabled by setting their bit in YWIN_ENA

to ‘1’ (bit [0] = YWIN0, [1] =

YWIN1

…).

Each of these windows is configured with an YWINi register that defines the position, size and sub-

sampling of the window. The 31 bits of each YWINi register span 4 physical SPI addresses. In the

table below, only the start address is given (the upper address being 21+4×i).

The readout direction of all windows can be changed from the default incrementing addresses (bottom

to top) to decrementing addresses (top to bottom) with the YWIN_DIR register. Using a different

setting for this register on both sides of the readout allows for reading out from center to edge or vice

versa.

Figure 93:

Vertical Windows Registers

Bank

Addr

Bits

Description

YWIN_ENA

28-29

[9:0]

One bit per window

0: Disable

1: Enable

YWIN_BLACK

[9:0]

One bit per

window to control the ‘Electrical Black’ mode

0: Disable

1: Enable

YWIN_DIR

[0:0]

Direction of readout addresses

0: Count upwards

1: Count downwards

YWINi.SIZE

18+4×i

[13:0]

Number of read out rows in window i

YWINi.START

18+4×i

[27:14]

Physical address of first row in window i

YWINi.SUBS

18+4×i

[30:28]

Row subsampling in window i

Ratio = 1/(2SUBS)

The START address of a window should comply with the values in Figure 92.

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