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CSG14K_CSG8K Datasheet(PDF) 88 Page - ams AG |
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CSG14K_CSG8K Datasheet(HTML) 88 Page - ams AG |
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88 / 113 page ![]() Document Feedback CSG14K_CSG8K Functional Description Datasheet • PUBLIC DS000571 • v1-00 • 2020-Dec-15 112 │ 87 Figure 107: Multiplexed Sub-LVDS Timing Example 7.6.3 Pixel Bit Order Figure 108: Output Bit Order Register Reg. Name Bank Addr Bits Description OUTP_BITORDER 0 10 [0] 0: Serial data is sent LSB first 1: Serial data is sent MSB first To accommodate different receiver systems, least or most significant bit of pixel data can be sent first (within the pixel word). This is independent from the chosen output format as it acts on the level of the pixel data. 7.7 Configuring the On-Chip Data Processing 7.7.1 Optical Black Clamping Figure 109: Optical Black Registers Reg. Name Bank Addr Bits Description EOB_TARGET 0 58-59 [12:0] Sets the target black level value in DN EOB_BYPASS 0 93 [0] 0: OBC on (recommended) 1: OBC off EOB_BYPASS_VALUE 0 94-95 [12:0] Sets the ideal black level at the ADC (when OBC off). This section explains how to set and correct the black levels. DVAL DATA0_OUT TP 760 TP TP TP 1260 TP TP TP 1760 TP TP TP 2260 TP TP DATA1_OUT DATA2_OUT DATA3_OUT 1259 1759 2259 2759 761 1261 1761 2261 762 1262 1762 2262 ... ... ... ... TP TP TP TP TP TP TP TP #1 #2 #3 #500 |
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