PI7C8150AND datasheet(36/111 Pages) PERICOM

36 / 111 page

PI7C8150A

2-PORT PCI-TO-PCI BRIDGE

Page 36 of 111

APRIL 2006 – Revision 1.1

For burst transfer, with the exception of “Memory Write and Invalidate” transactions,

the master latency timer expires and the PI7C8150A’s bus grant is de-asserted.

The target terminates the transaction with a retry, disconnect, or target abort.

If PI7C8150A is delivering posted write data when it terminates the transaction because the

master latency timer expires, it initiates another transaction to deliver the remaining write

data. The address of the transaction is updated to reflect the address of the current DWORD

to be delivered.

If PI7C8150A is pre-fetching read data when it terminates the transaction because the

master latency timer expires, it does not repeat the transaction to obtain more data.

3.8.2

MASTER ABORT RECEIVED BY PI7C8150A

If the initiator initiates a transaction on the target bus and does not detect DEVSEL_L

returned by the target within five clock cycles of the assertion of FRAME_L, PI7C8150A

terminates the transaction with a master abort. This sets the received-master-abort bit in the

status register corresponding to the target bus.

For delayed read and write transactions, PI7C8150A is able to reflect the master abort

condition back to the initiator. When PI7C8150A detects a master abort in response to a

delayed transaction, and when the initiator repeats the transaction, PI7C8150A does not

respond to the transaction with DEVSEL_L, which induces the master abort condition back

to the initiator. The transaction is then removed from the delayed transaction queue. When

a master abort is received in response to a posted write transaction, PI7C8150A discards

the posted write data and makes no more attempts to deliver the data. PI7C8150A sets the

received-master-abort bit in the status register when the master abort is received on the

primary bus, or it sets the received master abort bit in the secondary status register when

the master abort is received on the secondary interface. When master abort is detected in

posted write transaction with both master-abort-mode bit (bit 5 of bridge control register)

and the SERR_L enable bit (bit 8 of command register for secondary bus) are set,

PI7C8150A asserts P_SERR_L if the master-abort-on-posted-write is not set. The master-

abort-on-posted-write bit is bit 4 of the P_SERR_L event disable register (offset 64h).

Note: When PI7C8150A performs a Type 1 to special cycle conversion, a master abort is

the expected termination for the special cycle on the target bus. In this case, the master

abort received bit is not set, and the Type 1 configuration transaction is disconnected after

the first data phase.

3.8.3

TARGET TERMINATION RECEIVED BY PI7C8150A

When PI7C8150A initiates a transaction on the target bus and the target responds with

DEVSEL_L, the target can end the transaction with one of the following types of

termination:

Normal termination (upon de-assertion of FRAME_L)

Target retry

06-0057

PI7C8150AND Datasheet(PDF) 36 Page - Pericom Semiconductor Corporation

PI7C8150AND Datasheet(HTML) 36 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL