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PI7C8150AND Datasheet(PDF) 81 Page - Pericom Semiconductor Corporation |
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PI7C8150AND Datasheet(HTML) 81 Page - Pericom Semiconductor Corporation |
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81 / 111 page  PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 81 of 111 APRIL 2006 – Revision 1.1 14.1.9 HEADER TYPE REGISTER – OFFSET 0Ch Bit Function Type Description 23:16 Header Type R/O Read as 01h to indicate that the register layout conforms to the standard PCI-to-PCI bridge layout. 14.1.10 PRIMARY BUS NUMBER REGISTSER – OFFSET 18h Bit Function Type Description 7:0 Primary Bus Number R/W Indicates the number of the PCI bus to which the primary interface is connected. The value is set in software during configuration. Reset to 0 14.1.11 SECONDARY BUS NUMBER REGISTER – OFFSET 18h Bit Function Type Description 15:8 Secondary Bus Number R/W Indicates the number of the PCI bus to which the secondary interface is connected. The value is set in software during configuration. Reset to 0 14.1.12 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h Bit Function Type Description 23:16 Subordinate Bus Number R/W Indicates the number of the PCI bus with the highest number that is subordinate to the bridge. The value is set in software during configuration. Reset to 0 14.1.13 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h Bit Function Type Description 31:24 Secondary Latency Timer R/W Designated in units of PCI bus clocks. Latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. Reset to 0 14.1.14 I/O BASE REGISTER – OFFSET 1Ch Bit Function Type Description 3:0 32-bit Indicator R/O Read as 01h to indicate 32-bit I/O addressing 06-0057 |
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