 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PI7C8150AND Datasheet(PDF) 61 Page - Pericom Semiconductor Corporation |
|
|
|||||||||||||||||||||||||||||
PI7C8150AND Datasheet(HTML) 61 Page - Pericom Semiconductor Corporation |
|
|
61 / 111 page  PI7C8150A 2-PORT PCI-TO-PCI BRIDGE Page 61 of 111 APRIL 2006 – Revision 1.1 X = don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. Table 6-6 shows assertion of S_PERR_L that is set under the following conditions: PI7C8150A is either the target of a write transaction or the initiator of a read transaction on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. PI7C8150A detects a data parity error on the secondary bus or detects P_PERR_L asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus. Table 6-6. Assertion of S_PERR_L S_PERR_L Transaction Type Direction Bus Where Error Was Detected Primary/ Secondary Parity Error Response Bits 1 (de-asserted) Read Downstream Primary x / x 0 (asserted) Read Downstream Secondary x / 1 1 Read Upstream Primary x / x 1 Read Upstream Secondary x / x 1 Posted Write Downstream Primary x / x 1 Posted Write Downstream Secondary x / x 1 Posted Write Upstream Primary x / x 0 Posted Write Upstream Secondary x / 1 1 Delayed Write Downstream Primary x / x 1 Delayed Write Downstream Secondary x / x 0 2 Delayed Write Upstream Primary 1 / 1 0 Delayed Write Upstream Secondary x / 1 X = don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. Table 6-7 shows assertion of P_SERR_L. This signal is set under the following conditions: PI7C8150A has detected P_PERR_L asserted on an upstream posted write transaction or S_PERR_L asserted on a downstream posted write transaction. PI7C8150A did not detect the parity error as a target of the posted write transaction. The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. The SERR_L enable bit must be set in the command register. Table 6-7. Assertion of P_SERR_L for Data Parity Errors P_SERR_L Transaction Type Direction Bus Where Error Was Detected Primary / Secondary Parity Error Response Bits 1 (de-asserted) Read Downstream Primary x / x 1 Read Downstream Secondary x / x 1 Read Upstream Primary x / x 06-0057 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
