NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb Double Data Rate SDRAM
REV 1.1
12/2001
45
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Power-Down
Power-down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode
is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE.
The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior
to entering Power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur
before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at the
inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, power-down duration is limited by the refresh
requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled power-down
mode.
The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid,
executable command may be applied one clock cycle later.
Power Down
tIS
tIS
CK
CK
CKE
Command
No column
access in
progress
VALID
NOP
VALID
Don’t Care
Exit
power down
mode
Enter Power Down mode
(Burst Read or Write operation
must not be in progress)
NOP
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