MRF24J40-ISLASHML datasheet(40/151 Pages) MICROCHIP

40 / 151 page

MRF24J40

DS30009776E-page 40

Preliminary

 2021 Microchip Technology Inc.

TXPEND: TX DATA PENDING REGISTER (ADDRESS: 0x21)

R/W-1

R/W-0

R/W-1

R/W-0

MLIFS5

MLIFS4

MLIFS3

MLIFS2

MLIFS1

MLIFS0

GTSSWITCH

FPACK(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-2

MLIFS[5:0]: Minimum Long Interframe Spacing bits

The minimum number of symbols forming a Long Interframe Spacing (LIFS) period. Refer to

IEEE 802.15.4™-2003 Standard, Section 7.5.1.2 “IFS” and Table 70: MAC Sublayer Constants.

MLIFS + RFSTBL = aMinLIFSPeriod = 40 symbols.

Units: symbol period (16

s). Default value: 0x21. Recommended values: MLIFS = 0x1F and

RFSTBL = 0x9.

bit 1

GTSSWITCH: Continue TX GTS FIFO Switch in CFP bit

1 = GTS1 and GTS2 FIFO will toggle with each other during CFP

0 = GTS1 and GTS2 FIFO will stop toggling with each other if the transmission fails (default)

bit 0

FPACK: Frame Pending bit in the Acknowledgement Frame bit(1)

Sets or clears the frame pending bit in the Acknowledgement frame.

1 = Sets frame pending bit

0 = Clears frame pending bit

Note 1: Refer to IEEE 802.15.4™-2003 Standard, Section 7.2.1.1.3 “Frame Pending Subfield” and

Section 7.2.2.3.1 “Acknowledgement Frame MHR Fields”.

MRF24J40-I/ML Datasheet(PDF) 40 Page - Microchip Technology

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