UPD78323LP datasheet(32/88 Pages) RENESAS

32 / 88 page

µPD78323, 78324

BLOCK FUNCTIONS

3.1

BUS CONTROL UNIT (BCU)

In the BCU, the necessary bus cycle is started according to the physical address obtained by the execution unit (EXU).

If no bus cycle startup request is made from the EXU, a prefetch address is generated and instruction prefetch is carried

out. The prefetched instruction code is fetched into the instruction queue.

3.2

EXECUTION UNIT (EXU)

In the EXU, address calculation, arithmetic logical operation and data transfer are controlled by microprograms. A 256-

byte RAM is built in the EXU.

The 256-byte RAM in the EXU is accessible by the relevant instruction faster than peripheral RAM (768 bytes).

3.3

ROM/RAM

This block consists of a 32K-byte ROM and a 768-byte RAM. However, the

µPD78323 does not incorporate ROM.

ROM access can be disabled by EA pin.

3.4

INTERRUPT CONTROLLER

Various interrupt requests (NMI, INTP0 to INTP6) generated either externally or from the peripheral hardware are

processed by the context switch, vectored interrupt or macro service function.

The 3-level interrupt priority is also specified.

UPD78323LP Datasheet(PDF) 32 Page - Renesas Technology Corp