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TAS5504 Datasheet(PDF) 19 Page - Texas Instruments

Part # TAS5504
Description  4 Channel Digital Audio PWM Processor
PDF  96 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5504 Datasheet(HTML) 19 Page - Texas Instruments

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Introduction
11
SLES123 − October 2004
TAS5504
Coeff = 0 (lin)
(I2C 0x4F)
(I2C 0x50)
Coeff = 1 (lin)
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
IP Mixer 1
(I2C 0x41)
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
IP Mixer 2
(I2C 0x42)
IP Mixer 3
(I2C 0x47)
IP Mixer 4
(I2C 0x48)
Coeff = 0 (lin)
(I2C 0x4A)
Coeff = 0 (lin)
(I2C 0x49)
Coeff = 0 (lin)
(I2C 0x4C)
Coeff = 1 (lin)
(I2C 0x4D)
Coeff = 0 (lin)
(I2C 0x4B)
Coeff = 0 (lin)
(I2C 0x4E)
SDIN1−L(L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
Bass &
Treble 1
(0xDA−
0xDD)
L to
PWM1
OP Mixer 1
(I2C 0xAA)
4X2 Output
Mixer
7 DAP1
BQ
(0x51−
0x57)
Loud−
ness
(0x91−
0x95)
DRC1
(0x96−
0x9C)
Bass &
Treble 1
(0xDA−
0xDD)
R to
PWM2
OP Mixer 2
(I2C 0xAB)
Mixer
7 DAP2
BQ
(0x58−
0x5E)
Loud−
ness
(0x91−
0x95)
DRC1
(0x96−
0x9C)
Bass &
Treble 1
(0xDA−
0xDD)
C to
PWM3
OP Mixer 3
(I2C 0xB0)
Mixer
5 DAP3
BQ
(0x7D−
0x81)
Loud−
ness
(0x91−
0x95)
DRC1
(0x96−
0x9C)
Bass &
Treble 4
(0xDA−
0xDD)
Sub to
PWM4
OP Mixer 4
(I2C 0xB1)
Mixer
5 DAP4
BQ
(0x84−
0x88)
Loud−
ness
(0x91−
0x95)
DRC2
(0x9D−
0xA1)
2 DAP3
BQ
(0x7B−
0x7C)
2 DAP4
BQ
(0x82−
0x83)
DAP1
Volume
(0xD1)
Master Vol
(0xD9)
DAP2
Volume
(0xD2)
Master Vol
(0xD9)
DAP3
Volume
(0xD7)
Master Vol
(0xD9)
DAP4
Volume
(0xD8)
Master Vol
(0xD9)
Max Vol
Max Vol
Max Vol
Max Vol
Default Input is BOLD
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
SDIN4−L(C)
SDIN4−R (LFE)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
SDIN4−L (C)
SDIN4−R(LFE)
4X2 Output
4X2 Output
4X2 Output
Figure 1−2. TAS5504 DAP Architecture With I2C Registers (Fs ≤ 96 kHz)
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
IP Mixer 1
(I2C 0x41)
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
IP Mixer 2
(I2C 0x42)
IP Mixer 3
(I2C 0x47)
IP Mixer 4
(I2C 0x48)
SDIN1−Lt (L)
SDIN1−Rt (R)
SDIN2−Lt (LS)
SDIN2−Rt (RS)
SDIN3−Lt (LBS)
SDIN3−Rt (RBS)
SDIN4−Lt (C)
SDIN4−Rt (LFE)
SDIN1−Lt (L)
SDIN1−Rt (R)
SDIN2−Lt (LS)
SDIN2−Rt (RS)
SDIN3−Lt (LBS)
SDIN3−Rt (RBS)
SDIN4−Lt (C)
SDIN4−Rt (LFE)
SDIN1−Lt (L)
SDIN1−Rt (R)
SDIN2−Lt (LS)
SDIN2−Rt (RS)
SDIN3−Lt (LBS)
SDIN3−Rt (RBS)
SDIN4−Lt (C)
SDIN4−Rt (LFE)
SDIN1−Lt (L)
SDIN1−Rt (R)
SDIN2−Lt (LS)
SDIN2−Rt (RS)
SDIN3−Lt (LBS)
SDIN3−Rt (RBS)
SDIN4−Lt (C)
SDIN4−Rt (LFE)
Bass &
Treble 1
(0xDA−
0xDD)
L to
PWM1
OP Mixer 1
(I2C 0xAA)
Mixer
7 DAP1
BQ
(0x51−
0x57)
Loud−
ness
(0x91−
0x95)
DRC1
(0x96−
0x9C)
Bass &
Treble 1
(0xDA−
0xDD)
R to
PWM2
OP Mixer 2
(I2C 0xAB)
Mixer
7 DAP2
BQ
(0x58−
0x5E)
Loud−
ness
(0x91−
0x95)
DRC1
(0x96−
0x9C)
C to
PWM3
OP Mixer 3
(I2C 0xB0)
Mixer
Bass &
Treble 4
(0xDA−
0xDD)
Sub to
PWM4
OP Mixer 4
(I2C 0xB1)
Mixer
7 DAP4
BQ
(0x82−
0x88)
Loud−
ness
(0x91−
0x95)
DRC2
(0x9D−
0xA1)
DAP1
Volume
(0xD1)
Master Vol
(0xD9)
DAP2
Volume
(0xD2)
Master Vol
(0xD9)
DAP4
Volume
(0xD8)
Master Vol
(0xD9)
Max Vol
Max Vol
Max Vol
Master Vol
(0xD9)
4X2 Output
4X2 Output
4X3 Output
4X3 Output
Figure 1−3. TAS5504 Architecture With I2C Registers (Fs = 176.4 kHz or Fs = 192 kHz)



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