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ES9028Q2M Datasheet(PDF) 4 Page - ESS Technology,Inc |
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ES9028Q2M Datasheet(HTML) 4 Page - ESS Technology,Inc |
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4 / 45 page  0.41 January 16, 2020 ES9028Q2M Datasheet ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643- 8800 • WWW.ESSTECH.COM 4 PIN DESCRIPTIONS Pin Name Pin Type Reset State Pin Description 1 ADDR I Tri-stated I2C Address Select 2 DMODE I - Bus type select: 1'b0 for normal serial mode, 1'b1 => SLIMbus mode 3 VCCA Power Power Analog +3.3V for OSC 4 XOUT AO Floating XTAL Output 5 XI (MCLK) AI Floating XTAL / MCLK Input 6 AGND Ground Ground Analog Ground 7 AGND_R Ground Ground Analog Ground for the Right Channel 8 AVCC_R Power Power Analog AVCC for the Right Channel 9 DACRB AO Driven to ground Differential Negative Output for the Right Channel 10 DACR AO Driven to ground Differential Positive Output for the Right Channel 11 BIAS O 1’b0 General I/O. Controlled by software 12 SW O 1’b0 General I/O. Can be connected to switch input of SABRE9602 13 FSYNC O - General I/O. Can be connected to FSYNC of SABRE9602 14 HPSDb O 1’b0 General I/O. Controlled by software. Can be connected to Headphone Shutdown of SABRE9602 15 DACL AO Driven to ground Differential Positive Output for the Left Channel 16 DACLB AO Driven to ground Differential Negative Output for the Left Channel 17 NC - - No internal connection. May be grounded if desired 18 AVCC_L Power Power Analog AVCC for the Left Channel 19 AGND_L Ground Ground Analog Ground for the Left Channel 20 VCCA Power Power Analog +3.3V for OSC 21 DVCC Power Power Digital +1.8V to +3.3V 22 DGND Ground Ground Digital Ground 23 DVDD Power (Internal / External) Power Digital Core Voltage, nominally +1.2V, is supplied by a regulator from DVCC. DVDD should be decoupled with a minimum 4.7 F capacitor to DGND. DVDD needs to be externally supplied for high XI / MCLK frequency. Please refer to the section about the DVDD supply on page 8 for additional information. 24 GPIO2 I/O Tri-stated GPIO 2 25 GPIO1 I/O Tri-stated GPIO 1 26 DATA2 I Tri-stated DSD Data2 (R) or PCM Data CH1/CH2 or SPDIF Input 2 27 DATA1 I/O Tri-stated Master mode off: Input for DSD Data1 (L) or PCM Frame Clock or SPDIF Input 3 Master mode on: Output for PCM Frame Clock 28 DATA_CLK I/O Tri-stated Master mode off: Input for PCM Bit Clock or DSD Bit Clock or SPDIF Input 1 Master mode on: Output for PCM Bit Clock 29 RESETB I Tri-stated Master Reset / Power Down (active low) 30 DGND Ground Ground Digital Ground 31 SCL I Tri-stated I2C Serial Clock Input 32 SDA I/O Tri-stated I2C Serial Data Input/Output Exposed Pad AGND Ground Ground The exposed pad must be connected to Analog Ground |
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