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January 16, 2020

ES9028Q2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-

8800 • WWW.ESSTECH.COM

8

System Clock (XI / MCLK)

A system clock is required for proper operation of the digital filters and modulation circuitry. See page 34, Note 2 for the

maximum MCLK frequencies supported. The minimum system clock frequency must also satisfy:

Data Type

Minimum MCLK Frequency

Note

DSD Data

MCLK > 3 x FSR , FSR = 2.8224MHz (x 1, 2 or 4)

The maximum FSR frequency

is further limited by the

maximum MCLK frequencies

supported as shown on page

34, Note 2.

Serial Normal Mode

MCLK > 192 x FSR, FSR

 384kHz

MCLK = 128 x FSR (synchronous MCLK) with FSR

 384kHz

Serial OSF Bypass Mode

MCLK > 24 x FSR, FSR

 1.536MHz

SPDIF Data

MCLK > 386 x FSR, FSR

 200kHz

Data Clock

DATA_CLOCK must be (2 x i2s_length) x FSR for SERIAL, and FSR for DSD modes. For SPDIF mode, this pin is used for

SPDIF input. The DATA_CLK pin should be pulled low if not used.

Built-in Digital Filters

Three digital filters are included for PCM data, a fast roll-off filter, a slow roll-off filter, and a minimum phase filter. See 'PCM

Filter Characteristics' for more information.

Standby Mode

For lowest power consumption, the following should be performed to enter the stand-by mode:

•

Set the soft_start bit in register 14 to 1'b0 to ramp the DAC outputs (DACL, DACLB, DACR, DACRB) to ground.

•

RESETB pin should be brought to low digital level to:

o

Shut off the DACs, Oscillator and internal regulator.

o

Force digital I/O pins (DATA_CLK, DATA1, GPIO1, GPIO2, SDA ) into tri-state mode

o

Reset all registers to default states

•

If XI/MCLK is supplied externally, it should be stopped at a logic low level

•

If DVDD is supplied by an external regulator, it should be shut down during standby.

To resume from standby mode, bring RESETB to high digital level and reinitialize all registers.

DVDD Supply

The ES9028Q2M is equipped with a regulated DVDD supply powered from DVCC. The internal DVDD regulator must be

decoupled to DGND with a capacitor that maintains a minimum value of 1

F at 1.2V over the target operating temperature

range. The recommended capacitor for decoupling DVDD is a 4.7

F ±20%, X5R 6.3V 0402.

•

The internal DVDD should be used except under the following conditions:

1. PCM (SPDIF, I2S with OSF Bypass off or on) with MCLK > 50MHz or FSR > 192kHz

2. DSD with MCLK > 50MHz or FSR > 11.2MHz

•

Please refer to page 31, Note 2 for the maximum supported MCLK frequencies.

An External DVDD (+1.3V

5%) supply must be used above those frequencies.

The external supply voltage should be greater than the internal supply of +1.2V so the internal regulator is disabled.

SLIMbus Mode

The ES9028Q2M supports the Serial Low-power Inter-chip Media Bus (SLIMbus) standard, which is a common interface

between application processors and peripheral components in mobile devices. SLIMbus is implemented as a synchronous 2-

wire configurable interface. The ES9028Q2M acts as a slave device on the SLIMbus interface, relying on a master to be

present to generate clocks and frames.

To enable the SLIMbus mode the DMODE pin is pulled high. When DMODE is high, the DATA_CLK pin becomes

SLIMBUS_CLK and the DATA_2 pin becomes SLIMBUS_DATA. The ES9028Q2M now reports itself as 3 valid SLIMbus

devices if a valid clock and framer exist.