ES9028Q2M datasheet(13/45 Pages) ESS

13 / 45 page

January 16, 2020

0.41

ES9028Q2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-

8800 • WWW.ESSTECH.COM

8 bit, Read-Write Register, Default = 0x00

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

osc_drv

reserved *

soft_reset

Default

Bit

Mnemonic

Description

[7:4]

osc_drv

Oscillator drive specifies the bias current to the oscillator pad.

•

4'b0000: full bias (default)

•

4'b1000: 3/4 bias

•

4'b1100: 1/2 bias

•

4'b1110: 1/4 bias

•

4'b1111: shut down the oscillator

•

Other settings: reserved

It is recommended to use the default setting.

[3:1]

reserved *

[0]

soft_reset

1'b0 is normal operation (default)

1'b1 resets chip

* All Reserved Bits in Register #0 must be set to the indicated logic level to ensure correct device operation.

8 bit, Read-Write Register, Default = 0x8C

Bits

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Mnemonic

i2s_length

i2s_mode

auto_input_select

input_select

Default

Bit

Mnemonic

Description

[7:6]

i2s_length

2'd0 = 16bit

2'd1 = 24bit

2'd2 or 2'd3 = 32bit (default)

[5:4]

i2s_mode

2’d0 = I2S (default)

2’d1 = LJ mode

2’d2 = I2S

2’d3 = LJ mode

[3:2]

auto_input_select

2'd0 = 'input select',

2'd1 = I2S or DSD,

2'd2 = I2S or SPDIF,

2'd3 = I2S, SPDIF or DSD (default)

[1:0]

input_select

2'd0 = I2S (default)

2'd1 = SPDIF

2'd2 = reserved

2'd3 = DSD

ES9028Q2M Datasheet(PDF) 13 Page - ESS Technology,Inc

ES9028Q2M Datasheet(HTML) 13 Page - ESS Technology,Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL