ES9080 datasheet(4/146 Pages) ESS

4 / 146 page

CONFIDENTIAL ADVANCE INFORMATION 0.4.3

ES9080 Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

List of Figures

Figure 1 - ES9080 Block Diagram ....................................................................................................................................................................................6

Figure 2 - 40 QFN Pinout..................................................................................................................................................................................................7

Figure 3 - Digital signal path...........................................................................................................................................................................................10

Figure 4 - Example of using 8 channels of TDM showing both a 50/50 word select mode and a pulse word select mode. ..........................................14

Figure 5 - I2S & LJ Output Format..................................................................................................................................................................................15

Figure 6 - DSD Format ...................................................................................................................................................................................................15

Figure 7 - Clock Distribution Diagram with Registers .....................................................................................................................................................23

Figure 8 - Audio Interface Timing ...................................................................................................................................................................................27

Figure 9 - Functional Block Diagram of ES9080 APLL...................................................................................................................................................28

Figure 10 - Timing diagram for recommended power up sequence ...............................................................................................................................33

Figure 11 - Timing diagram for recommended power down sequence ..........................................................................................................................33

Figure 12 - I2C Slave Control Interface Timing ..............................................................................................................................................................39

Figure 13 - Reference schematic..................................................................................................................................................................................125

Figure 14 - Package dimensions ..................................................................................................................................................................................126

Figure 15 - Top view markings .....................................................................................................................................................................................127

Figure 16 - IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1) .......................................................................................................................128

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