| Electronic Components Datasheet Search |
|
ES9080 Datasheet(PDF) 49 Page - ESS Technology,Inc |
|
|
|||||||||||||||||||||||||||||
ES9080 Datasheet(HTML) 49 Page - ESS Technology,Inc |
|
49 / 146 page ![]() CONFIDENTIAL ADVANCE INFORMATION 0.4.3 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 49 ES9080 Product Datasheet Register 6: CP CLOCK DIV Bits [7:0] Default 8'd6 Bits Mnemonic Description [7:0] CP_CLK_DIV Specifies the clk divider for the CP clock source. Valid from 8'd0 to 8'd255. • 8’d6: Default • 8’dx: CP clock is SYS_CLK/((x+1)*2) Note: CP_CLK_DIV value should reflect a CP clock source frequency of between 500kHz-1MHz |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |