TLK2218ZPV datasheet(10/39 Pages) TI

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Miscellaneous Signals

TLK2218

SLLS734 – FEBRUARY 2007

SIGNAL

LOCATION

TYPE

DESCRIPTION

CODE

LVCMOS

Encode enable. When high, the 8b/10b encoder and decoder are enabled. The logic value of

input with

this terminal is logically ORed with MDIO register 17.7 (8b/10b_EN).

P/D

CV_DIS_EN

LVCMOS

Code violation/disparity error code enable. When CV_DIS_EN is high, the outputs RDxx[9:0]

input with

are set to 1 when a code violation or disparity error is detected. The logic value of this terminal

P/D

is logically ORed with the MDIO register 17.14 (CVDispEn).

This requires CODE to be enabled.o

RESET

LVCMOS

Chip reset (FIFO clear). Pulling this terminal high recenters the transmit skew buffers, recenters

input with

receive channel synchronization FIFOs, and resets MDIO flags.

P/D

LPBK

LVCMOS

Serial loopback enable. When asserted high, the outputs of the 8b/10b encoder are looped into

input with

the inputs of the 8b/10b decoder for each channel. The serial transmit outputs are driven to a

P/D

static state and the serial inputs are ignored.

MODE0

P11

LVCMOS

Configuration terminal. This terminal puts the device in full rate or half rate mode.

input with

MODE[0]

P/D

0 – Full rate mode

1 – Half rate mode

MODE1

P12

LVCMOS

Configuration terminal. This terminal puts the device under one of the following operation

input with

modes:

P/D

MODE[1]

0 – Multiplexed channel mode

1 – Nibble interface mode

ENABLE

D13

LVCMOS

Device enable. Pulling this terminal high enables all outputs of the device. A low on this

input with

terminal places all outputs for the device in the high-impedance state.

P/U

TCLKSEL

LVCMOS

Transfer clock select. This terminal controls clock selection mode between synchronized and

input

independent channel mode.

In independent channel mode (TCLKSEL = 1) channels are clocked in and out by independent

clocks TLCK[B:H] and RBC[A:H], respectively. In synchronized channel mode (TCLKSEL = 0)

transmit and receive clocks are centered around TCLKB and RCLK/RBCH.

The logic value of this signal is ORed with TransClkMode, MDIO register R17.15.

BUSYEN

LVCMOS

Busy mode enable. When asserted high, /K28.5/D10.1/ are treated as valid data and passed

input with

through the FIFO. When in the low state it causes high /K28.5/D10.1/ to be treated as an IDLE

P/U

sequence that can be deleted.

PLL_LOCK

R11

LVCMOS

PLL lock. When asserted high, this terminal provides an indication that sufficient time has

output

elapsed after a power-cycle or power-down sequence to ensure that PLLs have achieved lock.

GE_MOD

LVCMOS

Gigabit Ethernet mode. When driven high, the chip:

input

1) Treats /K28.5/ followed by any valid data character as an IDLE sequence, except that

when BMOD is asserted, the chip treats /K28.5/D10.1/ as described in the BMOD

terminal description.

2) Modifies IDLE to correct disparity by substituting /D5.6/ for /D16.2/ in a /K28.5/Dx.y/

transmit IDLE pair.

The logic value of the GE_MOD terminal is ORed with GEMODE register 24.15.

PRBSEN

C13

LVCMOS

PRBS enable. When this terminal is asserted high, the pseudorandom bit stream generator and

input with

comparator circuits are inserted into the transmit and receive data paths on all channels,

P/D

respectively.

If this terminal is not used it can be tied to the GND reference.

TX+/TX– are transmitting 27-1 PRBS. RX+/RX– are comparing incoming data to an internally

generated 27-1 PRBS. Results of the RX comparison can be read from the MDIO.

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