AS7030B datasheet(49/129 Pages) AMSCO

49 / 129 page

Document Feedback

AS7030B

Functional Description

Datasheet

• PUBLIC

DS000716

• v1-00 • 2020-Jun-10

128

│ 48

which can be pre-scaled with seq_div. The results of the analog to digital conversion are automatically

stored in a pipeline buffer or in register adc_data and the ADC FIFO.

The timings can be programmed with following registers (apply for man_mode=0):

Figure 40:

Timing Registers

Description

seq_div

Divider of the 1 µs input clock for all sequencer timings

seq_count

Number of measurements in one sequence

seq_start

Writing 1 starts the sequencer, 0 stops the sequencer

seq_period

Time of one measurement cycle

seq_led_start

Start time of the LED drivers within one cycle

seq_led_stop

Stop time of the LED drivers within one cycle

seq_secled_start

Start time of the secondary LED drivers within one cycle (used for SpO2)

seq_secled_stop

Stop time of the secondary LED drivers within one cycle (used for SpO2)

seq_itg_start

Start time of the integrator

seq_itg_stop

Stop time of the integrator

seq_sdp1_start

Start time of the synchronous demodulator’s 1 positive multiplication

seq_sdp1_stop

Stop time of the synchronous demodulator’s 1 positive multiplication

seq_sdm1_start

Start time of the synchronous

demodulator’s 1 negative multiplication

seq_sdm1_stop

Stop time of the synchronous demodulator’s 1 negative multiplication

seq_sdp2_start

Start time of the synchronous demodulator’s 2 positive multiplication

seq_sdp2_stop

Stop time of the synchronous

demodulator’s 2 positive multiplication

seq_sdm2_start

Start time of the synchronous demodulator’s 2 negative multiplication

seq_sdm2_stop

Stop time of the synchronous demodulator’s 2 negative multiplication

seq_adc

Sampling position of the ADC

seq_adc2tia,

seq_adc3tia

If the TIA channel is selected allow a second (and third) conversion within this cycle.

sd_subs,

sd_subs_always

Synchronous demodulator subsampling ratio between sequencer frequency and ADC sampling

frequency.

ulp

Ultra low power bit for the sequencer. If this bit is set and sd_subs>0, it disables the LED pulses

and powers off the TIA in all sequences but the one where the TIA is sampled. This bit can be

used to optimize the power consumption of the LEDs and the AS7030B (This bit is located in

ADC_CFGB Register bit 1)

irq_adc_timing_error

The sequencer setup caused a timing error on ADC conversion.

AS7030B Datasheet(PDF) 49 Page - ams AG

AS7030B Datasheet(HTML) 49 Page - ams AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL