Data Sheet

ADMV8505

REGISTER DETAILS

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Rev. 0 | 27 of 31

Table 30. Bit Descriptions for LUT0_FC

Bits

Bit Name

Description

Reset

Access

[7:0]

FC_LOAD_0

LUT 000: Center Frequency.

0x0

R/W

Address: 0x101, Reset: 0x00, Name: LUT0_BW

Table 31. Bit Descriptions for LUT0_BW

Bits

Bit Name

Description

Reset

Access

[7:0]

BW_LOAD_0

LUT 000: Bandwidth.

0x0

R/W

Address: 0x102, Reset: 0x00, Name: LUT0_MATCH

Table 32. Bit Descriptions for LUT0_MATCH

Bits

Bit Name

Description

Reset

Access

[7:0]

MATCH_LOAD_0

LUT 000: Match.

0x0

R/W

Address: 0x103 to 0x15F, Reset: 0x00

The LUT1 to LUT31 bit field functionality (Register 0x103 through Register 0x15F) is similar to LUT0 (Register 0x100 through Register 0x102),

see Table 12 for the register address information.

Address: 0x300, Reset: 0xC0, Name: INTERP_FC_Y0

Table 33. Bit Descriptions for INTERP_FC_Y0

Bits

Bit Name

Description

Reset

Access

[7:0]

INTERP_FC_Y0

Center Frequency Interpolation Point Y0.

0xC0

R/W

Address: 0x301, Reset: 0xA1, Name: INTERP_FC_Y1

Table 34. Bit Descriptions for INTERP_FC_Y1

Bits

Bit Name

Description

Reset

Access

[7:0]

INTERP_FC_Y1

Center Frequency Interpolation Point Y1.

0xA1

R/W