ADMV8505ACCZ-R7 datasheet(3/31 Pages) AD

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Data Sheet

ADMV8505

SPECIFICATIONS

analog.com

Rev. 0 | 3 of 31

TA = 25°C, unless otherwise noted.

Table 1. Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

FREQUENCY RANGE (fCENTER)

225

520

MHz

BANDWIDTH (3 dB)

BANDWIDTH ADJUSTABILITY

±2

RESOLUTION

8 bits per filter

REJECTION (20 dB)

Low-Side

0.84 × fCENTER

GHz

High-Side

1.19 × fCENTER

GHz

RE-ENTRY FREQUENCY

GHz

≤30 dB

INSERTION LOSS

4.5

RETURN LOSS

DYNAMIC PERFORMANCE

Input Compression (P0.1dB)

dBm

Input Third-Order Intercept (IP3)

Input power (PIN) is 10 dBm; f1 is Input Frequency 1 and

f2 is Input Frequency 2

Low-Side IP3

dBm

f1 = 0.9 × fCENTER , f2 = 0.95 × fCENTER

High-Side IP3

dBm

f1 = 1.05 × fCENTER , f2 = 1.1× fCENTER

In-Band IP3

dBm

f1 = fCENTER − 5 kHz, f2 = fCENTER + 5kHz

Group Delay

Measured at fCENTER = 225 MHz

Amplitude Settling Time

µs

To within ≤1 dB of static insertion loss

Phase Settling Time

µs

To within ≤2° of static phase

Drift Rate

At fCENTER = 365 MHz

Amplitude

−0.01

dB/°C

Frequency

−45

ppm/°C

SUPPLY VOLTAGE

VSS

–2.6

–2.5

–2.4

VDD

+3.2

+3.3

+3.4

SUPPLY CURRENT (STATIC)

Static

VSS Current (ISS)

−2

µA

VDD Current (IDD)

125

µA

Dynamic

IDD

fSCLK/4

Where fSCLK is the SCLK toggle frequency in MHz

For example, continuous serial peripheral interface (SPI)

writing at 10 MHz yields 2.5 mA of dynamic supply

current

LOGIC (RST, CS, SCLK, SDI, SDO, and SFL)

Logic Low

−0.3

+0.8

Logic High

+1.2

+3.3

+3.6

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