SRAM

SRAM

SRAM

SRAM

SRAM

AS5LC1008

Austin Semiconductor, Inc.

AS5LC1008

Rev. 1.0 11/02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

7

NOTES:

1. The internal write time is defined by the overlap of CE\ LOW and WE\ LOW. All signals must be in valid states to initiate a Write, but any one can go

inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE\ • V

IH

.

WRITE CYCLE #3 (WE\ Controlled, OE\ = LOW during Write Cycle)