SRAM

SRAM

SRAM

SRAM

SRAM

AS5LC1008

Austin Semiconductor, Inc.

AS5LC1008

Rev. 1.0 11/02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

4

A

NOTES:

1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1 output loading specified

in Figure 1.

2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

AC TEST CONDITIONS

PARAMETER

UNIT

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3ns

Input and Output timing and Reference Levels

1.5V

Output Load

See Figures 1 and 2

FIGURE 1

FIGURE 2

AC TEST LOADS

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

Read Cycle Time

10

---

12

---

15

---

20

---

ns

Address Access Time

---

10

---

12

---

15

---

20

ns

Output Hold time

2

---

2

---

2

---

2

---

ns

CE\ Access Time

---

10

---

12

---

15

---

20

ns

OE\ Access Time

---

5

---

6

---

7

---

8

ns

OE\ to Low-Z Output

2

0

---

0

---

0

---

0

---

ns

OE\ to High-Z Output

2

05060708

ns

CE\ to Low-Z Output

2

2

---

2

---

2

---

2

---

ns

CE\ to High-Z Output

2

05060708

ns

-10

-12

-20

-15