PSD835G2V_07 datasheet(20/118 Pages) STMICROELECTRONICS

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PSD architectural overview

PSD835G2V

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2.4

I/O Ports

The PSD has 52 I/O pins distributed over the seven ports (Port A, B, C, D, E, F and G). Each

I/O pin can be individually configured for different functions. Ports can be configured as

standard MCU I/O ports, PLD I/O, or latched address outputs for MCUs using multiplexed

address/data buses.

The JTAG pins can be enabled on Port E for In-System Programming (ISP). Ports F and G

can also be configured as data ports for a non-multiplexed bus.

Ports A and B can also be configured as a data port for a non-multiplexed bus.

2.5

MCU Bus Interface

PSD interfaces easily with most 8-bit MCUs that have either multiplexed or non-multiplexed

address/data buses. The device is configured to respond to the MCU’s control signals,

which are also used as inputs to the PLDs. For examples, please see MCU bus interface

examples on page 63.

2.6

JTAG Port

In-System Programming (ISP) can be performed through the JTAG signals on Port E. This

serial interface allows complete programming of the entire PSD device. A blank device can

be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can

be multiplexed with other functions on Port E. Table 3. on page 20 indicates the JTAG pin

assignments.

2.7

In-system programming (ISP)

Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can

be programmed or erased without the use of the MCU.

Table 2.

PLD I/O

Name

Inputs

Outputs

Product Terms

Decode PLD (DPLD)

Complex PLD (CPLD)

150

Table 3.

JTAG signals on Port E

Port E Pins

JTAG Signal

PE0

TMS

PE1

TCK

PE2

TDI

PE3

TDO

PE4

TSTAT

PE5

TERR

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