PSD835G2V_07 datasheet(39/118 Pages) STMICROELECTRONICS

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PSD835G2V

Programming Flash memory

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8.2

Data toggle

Checking the Toggle Flag (DQ6) bit is a method of determining whether a Program or Erase

cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm.

When the MCU issues a Program instruction, the embedded algorithm within the PSD

begins. The MCU then reads the location of the byte to be programmed in Flash memory to

check status. The Toggle Flag (DQ6) bit of this location toggles each time the MCU reads

this location until the embedded algorithm is complete. The MCU continues to read this

location, checking the Toggle Flag (DQ6) bit and monitoring the Error Flag (DQ5) bit. When

the Toggle Flag (DQ6) bit stops toggling (two consecutive reads yield the same value), and

the Error Flag (DQ5) bit remains 0, the embedded algorithm is complete. If the Error Flag

(DQ5) bit is 1, the MCU should test the Toggle Flag (DQ6) bit again, since the Toggle Flag

(DQ6) bit may have changed simultaneously with the Error Flag (DQ5) bit (see Figure 7).

The Error Flag (DQ5) bit is set if either an internal time-out occurred while the embedded

algorithm attempted to program the byte, or if the MCU attempted to program a 1 to a bit that

was not erased (not erased is logic 0).

It is suggested (as with all Flash memories) to read the location again after the embedded

programming algorithm has completed, to compare the Byte that was written to Flash

memory with the Byte that was intended to be written.

When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle

Flag (DQ6) bit toggles until the Erase cycle is complete. A 1 on the Error Flag (DQ5) bit

indicates a time-out condition on the Erase cycle; a 0 indicates no error. The MCU can read

any location within the sector being erased to get the Toggle Flag (DQ6) bit and the Error

Flag (DQ5) bit.

PSDsoft generates ANSI C code functions which implement these Data Toggling algorithms.

8.2.1

Unlock bypass

The Unlock Bypass instructions allow the system to program bytes to the Flash memories

faster than using the standard Program instruction. The Unlock Bypass mode is entered by

first initiating two Unlock cycles. This is followed by a third Write cycle containing the Unlock

Bypass code, 20h (as shown in Table 28. on page 32).

The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass

Program instruction is all that is required to program in this mode. The first cycle in this

instruction contains the Unlock Bypass Program code, A0h. The second cycle contains the

program address and data. Additional data is programmed in the same manner. These

instructions dispense with the initial two Unlock cycles required in the standard Program

instruction, resulting in faster total Flash memory programming.

During the Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass

Reset Flash instructions are valid.

To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset

Flash instruction. The first cycle must contain the data 90h; the second cycle, the data 00h.

Addresses are Don’t Care for both cycles. The Flash memory then returns to Read mode.

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