ADS6445 datasheet(55/75 Pages) STMICROELECTRONICS

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POWER DOWN MODES

Global Power Down

Channel Standby

Input Clock Stop

POWER SUPPLY SEQUENCING

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

Table 22. Minimum Clock Amplitude across gains

MINIMUM CLOCK AMPLITUDE SUPPORTED

CLOCK BUFFER GAIN

mVPP differential

Gain 0 (minimum gain)

800

Gain 1 (default gain)

400

Gain 2

300

Gain 3

200

Gain 4 (highest gain)

150

The ADS644X has three power down modes – global power down, channel standby and input clock stop.

This is a global power down mode in which almost the entire chip is powered down, including the four ADCs,

internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical

(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (refer to

Table 13). The output data and clock buffers are in high impedance state.

The wake-up time from this mode to data becoming valid in normal mode is 100

µs.

In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times.

Each of the four ADCs can be powered down independently using the register bits <PDN CH> (refer to

Table 13). The output LVDS buffers remain powered up.

The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.

The converter enters this mode:

• If the input clock frequency falls below 1 MSPS or

• If the input clock amplitude is less than 400 mV

PP, differential with default clock buffer gain setting) at any

sampling frequency.

All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time

from this mode to data becoming valid in normal mode is 100

µs.

Table 23. Power Down Modes Summary

AVDD POWER

LVDD POWER

POWER DOWN MODE

WAKE UP TIME

(mW)

In power-up

1360

297

–

Global power down

100

µs

1 Channel in standby

1115 (1)

297 (1)

200 Clocks

2 Channels in standby

825 (1)

297 (1)

200 Clocks

3 Channels in standby

532 (1)

297 (1)

200 Clocks

4 Channels in standby

245 (1)

297 (1)

200 Clocks

Input clock stop

200

100

µs

(1)

Sampling frequency = 125 MSPS.

During power-up, the AVDD and LVDD supplies can come up in any sequence. The two supplies are separated

inside the device. Externally, they can be driven from separate supplies or from a single supply.

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