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ADS6445 Datasheet(PDF) 64 Page - STMicroelectronics |
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ADS6445 Datasheet(HTML) 64 Page - STMicroelectronics |
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64 / 75 page ![]() www.ti.com CAPTURE TEST PATTERNS ADS6445, ADS6444 ADS6443, ADS6442 SLAS531 – MAY 2007 ADS644X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures sufficient setup/hold times for a reliable capture by the receiver. The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface, the SYNC pattern is 7 '1's followed by 7 '0's (from MSB to LSB). This information can be used by the receiver logic to shift the deserialized data till it matches the SYNC pattern. In addition to DESKEW and SYNC, the ADS644X includes other test patterns to verify correctness of the capture by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization and bit order. Table 25. Test Patterns PATTERN DESCRIPTION All zeros Outputs logic low. All ones Outputs logic high. Outputs toggle pattern - <D13-D0> alternates between 10101010101010 and Toggle 01010101010101 every clock cycle. Outputs a 14-bit custom pattern. The 14-bit custom pattern can be specified into two Custom serial interface registers. In the 2-wire interface, each code is sent over the 2 wires depending on the serialization and bit order. Sync Outputs a sync pattern. Outputs deskew pattern. Either <D13-D0> = 10101010101010 or <D11-D0> = Deskew 01010101010101 every clock cycle. Table 26. SYNC Pattern INTERFACE SERIALIZATION SYNC PATTERN ON EACH WIRE OPTION 14 X MSB-11111110000000-LSB 1-Wire 16 X MSB-111111111000000000-LSB 14 X MSB-1111000-LSB 2-Wire 16 X MSB-11110000-LSB 64 Submit Documentation Feedback |
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