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ADS6445 Datasheet(PDF) 56 Page - STMicroelectronics

Part # ADS6445
Description  QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
PDF  75 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ADS6445 Datasheet(HTML) 56 Page - STMicroelectronics

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DIGITAL OUTPUT INTERFACE
1-WIRE INTERFACE - 14
× AND 16× SERIALIZATION WITH DDR BIT CLOCK
ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
The ADS644X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of
these options can be easily programmed using either parallel pins or the serial interface.
The output interface options are:
• 1-Wire, 1× frame clock, 14× and 16× serialization with DDR bit clock
• 2-Wire, 1× frame clock, 16× serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise
• 2-Wire, 1× frame clock, 14× serialization, with SDR bit clock, byte wise/bit wise/word wise
• 2-Wire, (0.5 x) frame clock, 14× serialization, with DDR bit clock, byte wise/bit wise/word wise
The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface
options selected (refer to Table 12).
Table 24. Maximum Recommended Sampling Frequency for Different Output Interface Options
MAXIMUM
RECOMMENDED
BIT CLOCK
FRAME CLOCK
SERIAL DATA
INTERFACE OPTIONS
SAMPLING
FREQUENCY,
FREQUENCY, MHZ
RATE, Mbps
FREQUENCY,
MHZ
MSPS
14
× Serialization
65
455
65
910
DDR Bit
1-Wire
clock
16
× Serialization
65
520
65
1040
14
× Serialization
125
437.5
62.5
875
DDR Bit
2-Wire
clock
16
× Serialization
125
500
125
1000
14
× Serialization
65
455
65
910
SDR Bit
2-Wire
clock
16
× Serialization
65
520
65
1040
Each interface option is described in detail in the following sections.
Here the device outputs the data of each ADC serially on a single LVDS pair (1-wire). The data is available at
the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of
every frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data
rate is 14
× sample frequency (14× serialization) and 16 × sample frequency (16× serialization).
56
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