SST26VF032B-104ISLASHSM datasheet(18/82 Pages) MICROCHIP

18 / 82 page

SST26VF032B/SST26VF032BA

DS20005218K-page 18

 2013-2022 Microchip Technology Inc. and its subsidiaries

5.7

SPI Quad-Output Read

The SPI Quad-Output Read instruction supports fre-

quencies of up to 104 MHz from 2.7V-3.6V and up to 80

MHz from 2.3V-3.6V. SST26VF032B requires the IOC

bit in the Configuration register to be set to ‘1’ prior to

executing the command. Initiate SPI Quad-Output

Read by executing an 8-bit command, 6BH, followed

by address bits A[23:0] and a dummy byte. CE# must

remain active-low for the duration of the SPI Quad

Mode Read. See Figure 5-8 for the SPI Quad Output

Read sequence.

Following the dummy byte, the device outputs data

from SIO[3:0] starting from the specified address loca-

tion. The device continually streams data output

through all addresses until terminated by a low-to-high

transition on CE#. The internal Address Pointer auto-

matically increments until the highest memory address

is reached, at which point the Address Pointer returns

to the beginning of the address space.

FIGURE 5-8:

SPI QUAD OUTPUT READ

Note:

MSN= Most Significant Nibble, LSN = Least Significant Nibble

CE#

SIO0

SCK

012345678

31 32

MODE 3

MODE 0

15 16

6BH

39 40 41

A[23:16]

A[15:8]

A[7:0]

b4 b0

b5 b1

b6 b2

b7 b3

SIO1

SIO2

SIO3

Address

OP Code

Data

Byte 0

Dummy

Data

Byte N

SST26VF032B-104I/SM Datasheet(PDF) 18 Page - Microchip Technology

SST26VF032B-104I/SM Datasheet(HTML) 18 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL