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SST26VF032B-104I/SM Datasheet(PDF) 33 Page - Microchip Technology |
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SST26VF032B-104I/SM Datasheet(HTML) 33 Page - Microchip Technology |
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33 / 82 page ![]() 2013-2022 Microchip Technology Inc. and its subsidiaries DS20005218K-page 33 SST26VF032B/SST26VF032BA 5.31 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write- Enable Latch bit in the STATUS register to ‘1,’ allowing write operations to occur. The WREN instruction must be executed prior to any of the following operations: Sec- tor Erase, Block Erase, Chip Erase, Page Program, Program Security ID, Lockout Security ID, Write Block Protection Register, Lock-Down Block Protection Reg- ister, nonvolatile Write Lock Lock-Down Register, SPI Quad Page program, and Write STATUS Register. To execute a Write Enable the host drives CE# low then sends the Write Enable command cycle (06H) then drives CE# high. See Figure 5-32 and Figure 5-33 for the WREN instruction sequence. FIGURE 5-32: WRITE ENABLE SEQUENCE (SQI) FIGURE 5-33: WRITE ENABLE SEQUENCE (SPI) MODE 3 0 1 SCK SIO[3:0] CE# 06 MODE 0 CE# SI SCK 01 2 3 4 5 6 7 06 MODE 0 MODE 3 MSB |
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