7549 datasheet(13/73 Pages) RENESAS

13 / 73 page

Rev.2.00

Mar 05, 2007

Page 13 of 70

REJ03B0202-0200

7549 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Fig 9.

Memory map of special function register (SFR)

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

Port P0 (P0)

Port P0 direction register (P0D)

Port P1 (P1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Port P3 direction register (P3D)

Reserved

Port P0 drive capacity control register (DCCR)

Port P0 pull-up control register (PULL0)

Port P1 pull-up control register (PULL1)

Key-on wakeup input selection register (KEYS)

Capture/Compare register (low-order) (CRAL)

Capture/Compare register (high-order) (CRAH)

Capture/Compare register R/W pointer (CCRP)

Compare output mode register (CMOM)

Timer A (low-order) (TAL)

Timer A (high-order) (TAH)

Reserved

Transmit/Receive buffer register (TB/RB)

Serial I/O status register (SIOSTS)

Serial I/O control register (SIOCON)

UART control register (UARTCON)

Baud rate generator (BRG)

Reserved

Prescaler 12 (PRE12)

Timer 1 (T1)

Timer 2 (T2)

Timer mode register (TM)

Timer count source set register (TCSS)

Compare register re-load register (CMPR)

Capture/Compare port register (CCPR)

Capture/Compare status register (CCSR)

Compare interrupt source set register (CISR)

Capture software trigger register (CSTR)

Capture mode register (CAPM)

Reserved

AD control register (ADCON)

AD conversion register (low-order) (ADL)

AD conversion register (high-order) (ADH)

Clock mode register (CLKM)

Oscillation stop detection register (CLKSTP)

Watchdog timer control register (WDTCON)

Interrupt edge selection register (INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1 (IREQ1)

Interrupt request register 2 (IREQ2)

Interrupt control register 1 (ICON1)

Interrupt control register 2 (ICON2)

Note 1: Do not access to the reserved addresses.

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