7549 datasheet(28/73 Pages) RENESAS

28 / 73 page

Rev.2.00

Mar 05, 2007

Page 28 of 70

REJ03B0202-0200

7549 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

Fig 30. Structure of compare output mode register

Fig 31. Structure of capture/compare status register

Fig 32. Structure of compare interrupt source register

Compare output mode register

(CMOM: address 001316, initial value: 0016)

Compare 0 output level latch

0: Positive

1: Negative

Compare 1 output level latch

0: Positive

1: Negative

Compare 2 output level latch

0: Positive

1: Negative

Compare 0 trigger enable bit

0: Disabled

1: Enabled

Compare 1 trigger enable bit

0: Disabled

1: Enabled

Compare 2 trigger enable bit

0: Disabled

1: Enabled

Not used (returns “0” when read)

Capture/Compare status register

(CCSR: address 002F16, initial value: 0016)

Compare 0 output status bit

0: “L” level output

1: “H” level output

Compare 1 output status bit

0: “L” level output

1: “H” level output

Compare 2 output status bit

0: “L” level output

1: “H” level output

Capture 0 status bit

0: latch 00 captured

1: latch 01 captured

Not used (returns “0” when read)

Compare interrupt source register

(CISR: address 003016, initial value: 0016)

Compare latch 00 interrupt source bit

Compare latch 01 interrupt source bit

Compare latch 10 interrupt source bit

Compare latch 11 interrupt source bit

Compare latch 20 interrupt source bit

Compare latch 21 interrupt source bit

Not used (returns “0” when read)

0: Disabled

1: Enabled

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