PIC18F4685-ISLASHSP datasheet(360/484 Pages) MICROCHIP

360 / 484 page

PIC18F2682/2685/4682/4685

DS39761B-page 358

Preliminary

24.5

Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other PIC

devices.

The user program memory is divided into five blocks.

One of these is a boot block of 2 Kbytes. The remainder

of the memory is divided into four blocks on binary

boundaries.

Each of the five blocks has three code protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 24-5 shows the program memory organization

for 80- and 96-Kbyte devices and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 24-3.

FIGURE 24-5:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2682/2685/4682/4685

MEMORY SIZE/DEVICE

Block Code Protection

Controlled By:

80 Kbytes

(PIC18F2682/4682)

96 Kbytes

(PIC18F2685/4685)

Address

Range

Boot Block

000000h

0007FFh

CPB, WRTB, EBTRB

Block 0

000800h

003FFFh

CP0, WRT0, EBTR0

Block 1

004000h

007FFFh

CP1, WRT1, EBTR1

Block 2

008000h

00BFFFh

CP2, WRT2, EBTR2

Block 3

00C000h

00FFFFh

CP3, WRT3, EBTR3

Block 4

010000h

013FFFh

CP4, WRT4, EBTR4

Unimplemented

Read ‘0’s

Block 5

014000h

017FFFh

CP5, WRT5, EBTR5

Unimplemented

Read ‘0’s

Unimplemented

Read ‘0’s

018000h

1FFFFFh

(Unimplemented Memory Space)

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