PIC18F4685-ISLASHSP datasheet(361/484 Pages) MICROCHIP

361 / 484 page

Preliminary

DS39761B-page 359

PIC18F2682/2685/4682/4685

TABLE 24-3:

SUMMARY OF CODE PROTECTION REGISTERS

24.5.1

PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to or written from

any location using the table read and table write

instructions. The Device ID may be read with table

reads. The Configuration registers may be read and

written with the table read and table write instructions.

In normal execution mode, the CPn bits have no direct

effect. CPn bits inhibit external reads and writes. A

block of user memory may be protected from table

writes if the WRTn Configuration bit is ‘0’. The EBTRn

bits control table reads. For a block of user memory

with the EBTRn bit set to ‘0’, a table read instruction

that executes from within that block is allowed to read.

A table read instruction that executes from a location

outside of that block is not allowed to read and will

result in reading ‘0’s. Figures 24-6 through 24-8

illustrate table write and table read protection.

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

—

—CP5(1)

CP4

CP3

CP2

CP1

CP0

300009h

CONFIG5H

CPD

CPB

—

30000Ah

CONFIG6L

—

—WRT5(1)

WRT4

WRT3

WRT2

WRT1

WRT0

30000Bh

CONFIG6H

WRTD

WRTB

WRTC

—

30000Ch

CONFIG7L

—

EBTR5(1)

EBTR4

EBTR3

EBTR2

EBTR1

EBTR0

30000Dh

CONFIG7H

—

EBTRB

—

Legend: Shaded cells are unimplemented.

Note 1:

Unimplemented in PIC18F2682/4682 devices; maintain this bit set.

Note:

Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code

protection bits are only set to ‘1’ by a full

Chip Erase or Block Erase function. The

full Chip Erase and Block Erase functions

can only be initiated via ICSP or an

external programmer.

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