CS4525_07 datasheet(21/98 Pages) CIRRUS

21 / 98 page

DS726PP1

CS4525

SERIAL AUDIO INPUT PORT SWITCHING SPECIFICATIONS

AGND = DGND = PGND = 0 V; TA = 25°C; VD = 3.3 V; Inputs: Logic 0 = DGND; Logic 1 = VD.

Notes:

8. FCLK is the frequency of the crystal connected to the XTI/XTO pins or the input SYS_CLK signal.

9. Nbits is the number of bits per sample of the serial digital input.

10. After powering up the CS4525, RST should be held low until the power supplies and clocks are stable.

Parameters

Symbol

Min

Nominal

Max

Units

Supported Input Sample Rates

FSI

28.5

39.5

86.4

44.1

35.2

52.8

105.6

kHz

LRCK Duty Cycle

SCLK Frequency

(Note 8),(Note 9)

1/tp

FSI*2*Nbits

-FCLK/3

SCLK Duty Cycle

LRCK Setup Time Before SCLK Rising Edge

ts(LK-SK)

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

RST pin Low Pulse Width

(Note 10)

s(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDIN

s(LK-SK)

Figure 7. Serial Audio Input Port Timing

CS4525 Datasheet(PDF) 21 Page - Cirrus Logic

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