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ST72324BK Datasheet(PDF) 115 Page - STMicroelectronics |
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ST72324BK Datasheet(HTML) 115 Page - STMicroelectronics |
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115 / 188 page  ST72324B On-chip peripherals 115/188 10.5.5 Low power modes 10.5.6 Interrupts The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control bit is set and the interrupt mask in the CC register is reset (RIM instruction). 10.5.7 SCI registers SCI Status Register (SCISR) Table 59. Effect of low power modes on SCI Mode Description Wait No effect on SCI. SCI interrupts cause the device to exit from Wait mode. Halt SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. Table 60. SCI interrupt control/wake-up capability Interrupt event Event flag Enable control bit Exit from WAIT Exit from HALT Transmit data register empty TDRE TIE Yes No Transmission complete TC TCIE Yes No Received data ready to be read RDRF RIE Yes No Overrun error detected OR Yes No Idle line detected IDLE ILIE Yes No Parity error PE PIE Yes No SCISR Reset value: 1100 0000 (C0h) 7 654 32 10 TDRE TC RDRF IDLE OR NF FE PE RO RO RO RO RO RO RO RO Table 61. SCISR register description Bit Name Function 7 TDRE Transmit Data Register Empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a write to the SCIDR register). 0: Data is not transferred to the shift register. 1: Data is transferred to the shift register. Note: Data will not be transferred to the shift register unless the TDRE bit is cleared. |
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