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ST72324BK Datasheet(PDF) 16 Page - STMicroelectronics |
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ST72324BK Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 188 page  Register and memory map ST72324B 16/188 000Fh 0010h 0011h Port F(1) PFDR PFDDR PFOR Port F data register Port F data direction register Port F option register 00h(2) 00h 00h R/W R/W R/W 0012h to 0020h Reserved area (15 bytes) 0021h 0022h 0023h SPI SPIDR SPICR SPICSR SPI data I/O register SPI control register SPI control/status register xxh 0xh 00h R/W R/W R/W 0024h 0025h 0026h 0027h ITC ISPR0 ISPR1 ISPR2 ISPR3 Interrupt software priority register 0 Interrupt software priority register 1 Interrupt software priority register 2 Interrupt software priority register 3 FFh FFh FFh FFh R/W R/W R/W R/W 0028h EICR External interrupt control register 00h R/W 0029h Flash FCSR Flash control/status register 00h R/W 002Ah Watchdog WDGCR Watchdog control register 7Fh R/W 002Bh SI SICSR System integrity control/status register 000x 000xb R/W 002Ch 002Dh MCC MCCSR MCCBCR Main clock control/status register Main clock controller: beep control register 00h 00h R/W R/W 002Eh to 0030h Reserved area (3 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Timer A TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer A control register 2 Timer A control register 1 Timer A control/status register Timer A input capture 1 high register Timer A input capture 1 low register Timer A output compare 1 high register Timer A output compare 1 low register Timer A counter high register Timer A counter low register Timer A alternate counter high register Timer A alternate counter low register Timer A input capture 2 high register Timer A input capture 2 low register Timer A output compare 2 high register Timer A output compare 2 low register 00h 00h xxxx x0xxb xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read only Read only R/W R/W Read only Read only Read only Read only Read only Read only R/W R/W 0040h Reserved area (1 byte) Table 2. Hardware register map (continued) Address Block Register label Register name Reset status Remarks |
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