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ST72324BK Datasheet(PDF) 40 Page - STMicroelectronics |
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ST72324BK Datasheet(HTML) 40 Page - STMicroelectronics |
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40 / 188 page ![]() Interrupts ST72324B 40/188 Figure 21. Nested interrupt management 7.5 Interrupt registers 7.5.1 CPU CC register interrupt bits These two bits indicate the current interrupt software priority (see Table 15) and are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP instructions (see Table 17: Dedicated interrupt instruction set). Main IT2 TRAP Main IT0 3 2 1 3 3 3/0 3 11 00 01 11 11 11 RIM IT1 IT4 IT4 IT1 IT2 IT3 I1 I0 11 / 10 10 Software priority level CPU CC Reset value: 111x 1010(xAh) 7 654 32 10 11 I1 H I0 NZC R/W R/W R/W R/W R/W R/W R/W R/W Table 14. CPU CC register interrupt bits description Bit Name Function 5 I1 Software Interrupt Priority 1 3 I0 Software Interrupt Priority 0 Table 15. Interrupt software priority levels Interrupt software priority Level I1 I0 Level 0 (main) Low High 10 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable)(1) 1. TRAP and RESET events can interrupt a level 3 program. 11 |
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