ST72324BK datasheet(26/188 Pages) STMICROELECTRONICS

26 / 188 page

Supply, reset and clock management

ST72324B

26/188

Supply, reset and clock management

6.1

Introduction

The device includes a range of utility features for securing the application in critical

situations (for example in case of a power brown-out), and reducing the number of external

components. An overview is shown in Figure 12.

For more details, refer to dedicated parametric section.

Main features

●

Optional Phase Locked Loop (PLL) for multiplying the frequency by 2 (not to be used

with internal RC oscillator in order to respect the max. operating frequency)

●

Multi-Oscillator clock management (MO)

–

5 crystal/ceramic resonator oscillators

–

1 Internal RC oscillator

●

Reset Sequence Manager (RSM)

●

System Integrity management (SI)

–

Main supply low voltage detection (LVD)

–

Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main

supply

6.2

PLL (phase locked loop)

If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to

multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option

byte. If the PLL is disabled, then fOSC2 = fOSC/2.

Caution:

The PLL is not recommended for applications where timing accuracy is required.

Furthermore, it must not be used with the internal RC oscillator.

Figure 11.

PLL block diagram

PLL option bit

PLL x 2

fOSC2

/ 2

fOSC

ST72324BK Datasheet(PDF) 26 Page - STMicroelectronics

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