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ST72324BK Datasheet(PDF) 185 Page - STMicroelectronics |
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ST72324BK Datasheet(HTML) 185 Page - STMicroelectronics |
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185 / 188 page ![]() ST72324B Known limitations 185/188 As a consequence, for cycle-accurate operations, these configurations are prohibited in either input or output mode. Workaround To avoid this from occurring, it is recommended to connect one of these pins to GND (PF4 or PF0) or VDD (PA3 or PF1). Table 125. Port A and F configuration PLL PA3 PF4 PF1 PF0 Clock disturbance Off 010 Toggling Maximum 2 clock cycles lost at each rising or falling edge of PF0 On 0 1 0 1 Maximum 1 clock cycle lost out of every 16 |
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