ST72324BJ2 datasheet(119/188 Pages) STMICROELECTRONICS

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ST72324B

On-chip peripherals

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SCI Data Register (SCIDR)

This register contains the received or transmitted data character, depending on whether it is

read from or written to.

The Data register performs a double function (read and write) since it is composed of two

registers, one for transmission (TDR) and one for reception (RDR).

The TDR register provides the parallel interface between the internal bus and the output

shift register (see Figure 57). The RDR register provides the parallel interface between the

input shift register and the internal bus (see Figure 57).

3TE

Transmitter Enable

This bit enables the transmitter. It is set and cleared by software.

0: Transmitter is disabled

1: Transmitter is enabled

Notes:

- During transmission, a ‘0’ pulse on the TE bit (‘0’ followed by ‘1’) sends a preamble

(Idle line) after the current word.

- When TE is set there is a 1 bit-time delay before the transmission starts.

Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits

are both cleared (or if TE is never set).

2RE

Receiver Enable

This bit enables the receiver. It is set and cleared by software.

0: Receiver is disabled

1: Receiver is enabled and begins searching for a start bit

Note: Before selecting Mute mode (setting the RWU bit), the SCI must first receive

some data, otherwise it cannot function in Mute mode with Wake-Up by Idle line

detection.

1RWU

Receiver Wake-Up

This bit determines if the SCI is in mute mode or not. It is set and cleared by

software and can be cleared by hardware when a wake-up sequence is recognized.

0: Receiver in Active mode

1: Receiver in Mute mode

0SBK

Send Break

This bit set is used to send break characters. It is set and cleared by software.

0: No break character is transmitted.

1: Break characters are transmitted.

Note: If the SBK bit is set to ‘1’ and then to ‘0’, the transmitter will send a Break word

at the end of the current word.

SCIDR

Reset value: undefined

654

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

R/W

Table 63.

SCICR2 register description (continued)

Bit

Name

Function

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