ST72324BJ2 datasheet(118/188 Pages) STMICROELECTRONICS

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On-chip peripherals

ST72324B

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SCI Control Register 2 (SCICR2)

1PS

Parity Selection

This bit selects the odd or even parity when the parity generation/detection is

enabled (PCE bit set). It is set and cleared by software. The parity will be selected

after the current byte.

0: Even parity

1: Odd parity

0PIE

Parity Interrupt Enable

This bit enables the interrupt capability of the hardware parity control when a parity

error is detected (PE bit set). It is set and cleared by software.

0: Parity error interrupt disabled

1: Parity error interrupt enabled

SCICR2

Reset value: 0000 0000 (00h)

654

TIE

TCIE

RIE

ILIE

RWU

SBK

R/W

Table 63.

SCICR2 register description

Bit

Name

Function

7TIE

Transmitter Interrupt Enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register.

6TCIE

Transmission Complete Interrupt Enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC = 1 in the SCISR register.

5RIE

Receiver interrupt Enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR

4ILIE

Idle Line Interrupt Enable

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.

Table 62.

SCICR1 register description (continued)

Bit

Name

Function

ST72324BJ2 Datasheet(PDF) 118 Page - STMicroelectronics

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