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ST72324BJ2 Datasheet(PDF) 161 Page - STMicroelectronics |
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ST72324BJ2 Datasheet(HTML) 161 Page - STMicroelectronics |
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161 / 188 page ![]() ST72324B Electrical characteristics 161/188 12.12 Communication interface characteristics 12.12.1 Serial peripheral interface (SPI) The following characteristics are ubject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. The data is based on design simulation and/or characterization results, not tested in production. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. Refer to the I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Table 110. SPI characteristics Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency Master fCPU = 8 MHz fCPU/128 = 0.0625 fCPU/4 = 2 MHz Slave fCPU = 8 MHz 0 fCPU/2 = 4 tr(SCK) tf(SCK) SPI clock rise and fall time see I/O port pin description tsu(SS) (1) SS setup time(2) Slave tCPU +50 ns th(SS) (1) SS hold time Slave 120 tw(SCKH) (1) tw(SCKL) (1) SCK high and low time Master Slave 100 90 tsu(MI) (1) tsu(SI) (1) Data input setup time Master Slave 100 100 th(MI) (1) th(SI) (1) Data input hold time Master Slave 100 100 ta(SO) (1) Data output access time Slave 0 120 tdis(SO) (1) Data output disable time Slave 240 tv(SO) (1) Data output valid time Slave (after enable edge) 120 th(SO) (1) Data output hold time 0 tv(MO) (1) Data output valid time Master (after enable edge) 120 th(MO) (1) Data output hold time 0 1. Data based on design simulation and/or characterization results, not tested in production. 2. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU = 1 / fCPU = 125ns and tsu(SS) = 175ns. |
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